SoC verification

**Position :** SoC verification **Location** : Remote is fine **Must Requirement** : End\-to\-end UVM experience from scratch (across test bench infra development, debug, scoreboard etc.) Protocol experience like Ethernet, UCIe, PCIe is a plus but it is not mandatory like the end\-to\-end UVM expertise. **Key Responsibilities** * **Block\-Level Verification Ownership:** Take full technical ownership of verifying 4\-5 complex design blocks per project, ensuring high\-quality verification sign\-off. * **Testbench \& Component Development:** Build and maintain verification components, test sequences, agents, scoreboards, and functional coverage models from scratch using **System Verilog and UVM**. * **Verification Execution:** Execute directed and constrained\-random test scenarios, perform rigorous test debugging, and drive functional and code coverage closure. * **Protocol Application:** Apply deep working knowledge of advanced industry protocols such as **UCIe (Universal Chiplet Interconnect Express) 2\.0, PCIe, and Ethernet** to verify complex architectural features. * **Collaboration:** Interface smoothly with customer engineering teams and internal project leads, ensuring block\-level verification aligns with the customer\-owned top\-level testbench infrastructure. * **Debugging \& Triage:** Perform in\-depth waveform analysis, protocol debugging, root\-cause analysis, and regression triage using industry\-standard simulators. **Required Qualifications \& Skills** * **Experience:** 6 to 10\+ years of relevant hands\-on ASIC verification experience in complex digital designs. * **Methodologies:** Expert\-level proficiency in **SystemVerilog** and **UVM**, with a proven history of developing testbenches, test sequences, agents, and other components **from scratch**. * **Protocol Knowledge:** Hands\-on verification experience with one or more high\-speed protocols: * **UCIe (Universal Chiplet Interconnect Express) 2\.0** * **PCIe (Gen 4/5/6\)** * **Ethernet (MAC/PCS/PMA layers)** * **Domain Background:** Proven track record working on complex networking silicon, Switches, NICs, or high\-performance interconnect ASICs. * **Debugging Skills:** Strong expertise in waveform analysis, protocol debugging, root\-cause analysis, and regression triage using simulators (Synopsys VCS, Cadence Xcelium, or Mentor Questa). * **Soft Skills:** Strong problem\-solving abilities, solid communication skills, and the capability to work autonomously in a collaborative, customer\-facing environment. Pay: $60\.00 \- $70\.00 per hour Expected hours: 40\.0 per week Work Location: Remote